XT-26  Código del proyecto desarrollado en Sistemas Digitales II (SDII)
Antonio Julián Alférez Zamora & Sonsoles López Pernas
m5272.h
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1 /****************************************************************************/
2 /*
3  * m5272.h -- Motorola Coldfire 5272 Support
4  *
5  * (C) Copyright 2001, Key Technology (http://www.keyww.com)
6  */
7 
8 /****************************************************************************/
9 #ifndef m5272_h
10 #define m5272_h
11 /****************************************************************************/
12 
13 
14 /*
15  * Define master clock frequency of our 5272.
16  */
17 
18 #define MCF_CLK 66000000
19 
20 /*
21  * Place to put internal registers
22  */
23 
24 #define MCF_MBAR 0x10000000
25 #define mbar_readLong(x) *((volatile unsigned long *) (MCF_MBAR + x))
26 #define mbar_writeLong(x,y) *((volatile unsigned long *) (MCF_MBAR + x)) = y
27 #define mbar_readShort(x) *((volatile unsigned short *) (MCF_MBAR + x))
28 #define mbar_writeShort(x,y) *((volatile unsigned short *) (MCF_MBAR + x)) = y
29 #define mbar_readByte(x) *((volatile unsigned char *) (MCF_MBAR + x))
30 #define mbar_writeByte(x,y) *((volatile unsigned char *) (MCF_MBAR + x)) = y
31 
32 /* Rutinas de I/O de memoria */
33 #define escribe_byte(x,y) *((volatile unsigned char *) x) = y
34 #define lee_byte(x) *((volatile unsigned char *) x)
35 #define escribe_word(x,y) *((volatile unsigned short int *) x) = y
36 #define lee_word(x) *((volatile unsigned short int *) x)
37 #define escribe_long(x,y) *((volatile unsigned long int *) x) = y
38 #define lee_long(x) *((volatile unsigned long int *) x)
39 
40 /*
41  * Size of internal RAM
42  */
43 
44 #define INT_RAM_SIZE 4096
45 
46 /*
47  * Define the 5272 SIM register set addresses.
48  */
49 #define MCFSIM_SCR 0x04 /* System Configuration */
50 #define MCFSIM_SPR 0x06 /* System Protection */
51 #define MCFSIM_ICR1 0x20 /* Intr Ctrl reg 1 (r/w) */
52 #define MCFSIM_ICR2 0x24 /* Intr Ctrl reg 2 (r/w) */
53 #define MCFSIM_ICR3 0x28 /* Intr Ctrl reg 3 (r/w) */
54 #define MCFSIM_ICR4 0x2c /* Intr Ctrl reg 4 (r/w) */
55 
56 #define MCFSIM_PITR 0x34 /* Programmable Interrupt Transition */
57 #define MCFSIM_PIWR 0x38 /* Programmable Interrupt Wakeup */
58 #define MCFSIM_PIVR 0x3F /* Programmable Interrupt Vector */
59 
60 #define MCFSIM_PACNT 0x80 /* Port A Control (r/w) */
61 #define MCFSIM_PADDR 0x84 /* Port A Direction (r/w) */
62 #define MCFSIM_PADAT 0x86 /* Port A Value (r/w) */
63 #define MCFSIM_PBCNT 0x88 /* Port B Control */
64 #define MCFSIM_PBDDR 0x8C /* Port B Direction */
65 #define MCFSIM_PBDAT 0x8E /* Port B Value */
66 #define MCFSIM_PDCNT 0x98 /* Port D Control */
67 
68 #define MCFSIM_CSBR0 0x40 /* CS 0 Base reg (r/w) */
69 #define MCFSIM_CSOR0 0x44 /* CS 0 Option reg (r/w) */
70 #define MCFSIM_CSBR1 0x48 /* CS 1 Base reg (r/w) */
71 #define MCFSIM_CSOR1 0x4c /* CS 1 Option reg (r/w) */
72 #define MCFSIM_CSBR2 0x50 /* CS 2 Base reg (r/w) */
73 #define MCFSIM_CSOR2 0x54 /* CS 2 Option reg (r/w) */
74 #define MCFSIM_CSBR3 0x58 /* CS 3 Base reg (r/w) */
75 #define MCFSIM_CSOR3 0x5c /* CS 3 Option reg (r/w) */
76 #define MCFSIM_CSBR4 0x60 /* CS 4 Base reg (r/w) */
77 #define MCFSIM_CSOR4 0x64 /* CS 4 Option reg (r/w) */
78 #define MCFSIM_CSBR5 0x68 /* CS 5 Base reg (r/w) */
79 #define MCFSIM_CSOR5 0x6c /* CS 5 Option reg (r/w) */
80 #define MCFSIM_CSBR6 0x70 /* CS 6 Base reg (r/w) */
81 #define MCFSIM_CSOR6 0x74 /* CS 6 Option reg (r/w) */
82 #define MCFSIM_CSBR7 0x78 /* CS 7 Base reg (r/w) */
83 #define MCFSIM_CSOR7 0x7c /* CS 7 Option reg (r/w) */
84 
85 #define MCFSIM_SDCR 0x180 /* SDRAM Control Register */
86 #define MCFSIM_SDTR 0x184 /* SDRAM Control Register */
87 
88 /*******************************************/
89 /* Registros del mdulo Fast Ethernet */
90 /*******************************************/
91 
92 #define MCFSIM_MALR 0xC00
93 #define MCFSIM_MAUR 0xC04
94 
95 /*******************************************/
96 /* Registros del modulo de temporizacion */
97 /*******************************************/
98 
99 #define MCFSIM_TMR0 0x200
100 #define MCFSIM_TRR0 0x204
101 #define MCFSIM_TCR0 0x208
102 #define MCFSIM_TCN0 0x20C
103 #define MCFSIM_TER0 0x210
104 #define MCFSIM_TMR1 0x220
105 #define MCFSIM_TRR1 0x224
106 #define MCFSIM_TCR1 0x228
107 #define MCFSIM_TCN1 0x22C
108 #define MCFSIM_TER1 0x230
109 #define MCFSIM_TMR2 0x240
110 #define MCFSIM_TRR2 0x244
111 #define MCFSIM_TCR2 0x248
112 #define MCFSIM_TCN2 0x24C
113 #define MCFSIM_TER2 0x250
114 #define MCFSIM_TMR3 0x260
115 #define MCFSIM_TRR3 0x264
116 #define MCFSIM_TCR3 0x268
117 #define MCFSIM_TCN3 0x26C
118 #define MCFSIM_TER3 0x270
119 
120 /* Registros de control del Watchdog */
121 #define MCFSIM_WRRR 0x280
122 #define MCFSIM_WIRR 0x284
123 #define MCFSIM_WCR 0x288
124 #define MCFSIM_WER 0x28C
125 
126 
127 /*******************************************/
128 /* Registros del modulo PWM */
129 /*******************************************/
130 #define MCFSIM_PWCR0 0x00C0
131 #define MCFSIM_PWCR1 0x00C4
132 #define MCFSIM_PWCR2 0x00C8
133 #define MCFSIM_PWWD0 0x00D0
134 #define MCFSIM_PWWD1 0x00D4
135 #define MCFSIM_PWWD2 0x00D8
136 /* Correspondencia entre frecuencias y divisor a configurar */
137 /* Los mdulos PWM generan una seal con un periodo obtenido */
138 /* de dicidir la frecuencia de reloj del sistema (66 MHz) */
139 /* de la siguiente manera: */
140 /* */
141 /* Frec = (66 MHz) / 256*(2^(X)) ,, X = Divisor a configurar */
142 /* */
143 #define PWM_258KHZ 0x00
144 #define PWM_129KHZ 0x01
145 #define PWM_64KHZ 0x02
146 #define PWM_32KHZ 0x03
147 #define PWM_16KHZ 0x04
148 #define PWM_8KHZ 0x05
149 #define PWM_4KHZ 0x06
150 #define PWM_2KHZ 0x07
151 #define PWM_1KHZ 0x08
152 #define PWM_512HZ 0x09
153 #define PWM_258HZ 0x0A
154 #define PWM_129HZ 0x0B
155 #define PWM_66HZ 0x0C
156 #define PWM_34HZ 0x0D
157 #define PWM_17HZ 0x0E
158 #define PWM_9HZ 0x0F
159 
160 
161 
162 /*
163  * Macro to get and set IMR register. It is 16 bits on the 5272.
164  */
165 
166 #define BASE_PUERTO0 0x30000000 /* Direccion del puerto 0 */
167 #define BASE_PUERTO_S 0x40000000 /* Direccion del puerto S */
168 #define BASE_PUERTO_E 0x50000002 /* Direccion del puerto E */
169 
170 
171 /*******************************************/
172 /* Registros del modulo QSPI */
173 /*******************************************/
174 #define MCFSIM_QMR 0x00A0 /* modo */
175 #define MCFSIM_QDLYR 0x00A4 /* retardo */
176 #define MCFSIM_QWR 0x00A8 /* wrap */
177 #define MCFSIM_QIR 0x00aC /* interrupcin */
178 #define MCFSIM_QAR 0x00B0 /* direccin */
179 #define MCFSIM_QDR 0x00B4 /* dato */
180 
181 #define QSPI_TX_RAM_START 0x00
182 #define QSPI_RX_RAM_START 0x10
183 #define QSPI_COMMAND_RAM_START 0x20
184 
185 
186 
187 
188 
189 /****************************************************************************/
190 #endif /* m5272_h */
191 
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