XT-26
Código del proyecto desarrollado en Sistemas Digitales II (SDII)
Antonio Julián Alférez Zamora & Sonsoles López Pernas
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m5272.h
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/****************************************************************************/
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/*
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* m5272.h -- Motorola Coldfire 5272 Support
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*
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* (C) Copyright 2001, Key Technology (http://www.keyww.com)
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*/
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/****************************************************************************/
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#ifndef m5272_h
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#define m5272_h
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/****************************************************************************/
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/*
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* Define master clock frequency of our 5272.
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*/
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#define MCF_CLK 66000000
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/*
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* Place to put internal registers
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*/
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#define MCF_MBAR 0x10000000
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#define mbar_readLong(x) *((volatile unsigned long *) (MCF_MBAR + x))
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#define mbar_writeLong(x,y) *((volatile unsigned long *) (MCF_MBAR + x)) = y
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#define mbar_readShort(x) *((volatile unsigned short *) (MCF_MBAR + x))
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#define mbar_writeShort(x,y) *((volatile unsigned short *) (MCF_MBAR + x)) = y
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#define mbar_readByte(x) *((volatile unsigned char *) (MCF_MBAR + x))
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#define mbar_writeByte(x,y) *((volatile unsigned char *) (MCF_MBAR + x)) = y
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/* Rutinas de I/O de memoria */
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#define escribe_byte(x,y) *((volatile unsigned char *) x) = y
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#define lee_byte(x) *((volatile unsigned char *) x)
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#define escribe_word(x,y) *((volatile unsigned short int *) x) = y
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#define lee_word(x) *((volatile unsigned short int *) x)
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#define escribe_long(x,y) *((volatile unsigned long int *) x) = y
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#define lee_long(x) *((volatile unsigned long int *) x)
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/*
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* Size of internal RAM
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*/
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#define INT_RAM_SIZE 4096
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/*
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* Define the 5272 SIM register set addresses.
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*/
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#define MCFSIM_SCR 0x04
/* System Configuration */
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#define MCFSIM_SPR 0x06
/* System Protection */
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#define MCFSIM_ICR1 0x20
/* Intr Ctrl reg 1 (r/w) */
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#define MCFSIM_ICR2 0x24
/* Intr Ctrl reg 2 (r/w) */
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#define MCFSIM_ICR3 0x28
/* Intr Ctrl reg 3 (r/w) */
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#define MCFSIM_ICR4 0x2c
/* Intr Ctrl reg 4 (r/w) */
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#define MCFSIM_PITR 0x34
/* Programmable Interrupt Transition */
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#define MCFSIM_PIWR 0x38
/* Programmable Interrupt Wakeup */
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#define MCFSIM_PIVR 0x3F
/* Programmable Interrupt Vector */
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#define MCFSIM_PACNT 0x80
/* Port A Control (r/w) */
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#define MCFSIM_PADDR 0x84
/* Port A Direction (r/w) */
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#define MCFSIM_PADAT 0x86
/* Port A Value (r/w) */
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#define MCFSIM_PBCNT 0x88
/* Port B Control */
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#define MCFSIM_PBDDR 0x8C
/* Port B Direction */
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#define MCFSIM_PBDAT 0x8E
/* Port B Value */
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#define MCFSIM_PDCNT 0x98
/* Port D Control */
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#define MCFSIM_CSBR0 0x40
/* CS 0 Base reg (r/w) */
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#define MCFSIM_CSOR0 0x44
/* CS 0 Option reg (r/w) */
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#define MCFSIM_CSBR1 0x48
/* CS 1 Base reg (r/w) */
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#define MCFSIM_CSOR1 0x4c
/* CS 1 Option reg (r/w) */
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#define MCFSIM_CSBR2 0x50
/* CS 2 Base reg (r/w) */
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#define MCFSIM_CSOR2 0x54
/* CS 2 Option reg (r/w) */
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#define MCFSIM_CSBR3 0x58
/* CS 3 Base reg (r/w) */
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#define MCFSIM_CSOR3 0x5c
/* CS 3 Option reg (r/w) */
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#define MCFSIM_CSBR4 0x60
/* CS 4 Base reg (r/w) */
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#define MCFSIM_CSOR4 0x64
/* CS 4 Option reg (r/w) */
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#define MCFSIM_CSBR5 0x68
/* CS 5 Base reg (r/w) */
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#define MCFSIM_CSOR5 0x6c
/* CS 5 Option reg (r/w) */
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#define MCFSIM_CSBR6 0x70
/* CS 6 Base reg (r/w) */
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#define MCFSIM_CSOR6 0x74
/* CS 6 Option reg (r/w) */
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#define MCFSIM_CSBR7 0x78
/* CS 7 Base reg (r/w) */
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#define MCFSIM_CSOR7 0x7c
/* CS 7 Option reg (r/w) */
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#define MCFSIM_SDCR 0x180
/* SDRAM Control Register */
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#define MCFSIM_SDTR 0x184
/* SDRAM Control Register */
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/*******************************************/
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/* Registros del módulo Fast Ethernet */
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/*******************************************/
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#define MCFSIM_MALR 0xC00
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#define MCFSIM_MAUR 0xC04
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/*******************************************/
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/* Registros del modulo de temporizacion */
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/*******************************************/
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#define MCFSIM_TMR0 0x200
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#define MCFSIM_TRR0 0x204
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#define MCFSIM_TCR0 0x208
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#define MCFSIM_TCN0 0x20C
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#define MCFSIM_TER0 0x210
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#define MCFSIM_TMR1 0x220
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#define MCFSIM_TRR1 0x224
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#define MCFSIM_TCR1 0x228
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#define MCFSIM_TCN1 0x22C
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#define MCFSIM_TER1 0x230
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#define MCFSIM_TMR2 0x240
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#define MCFSIM_TRR2 0x244
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#define MCFSIM_TCR2 0x248
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#define MCFSIM_TCN2 0x24C
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#define MCFSIM_TER2 0x250
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#define MCFSIM_TMR3 0x260
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#define MCFSIM_TRR3 0x264
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#define MCFSIM_TCR3 0x268
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#define MCFSIM_TCN3 0x26C
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#define MCFSIM_TER3 0x270
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/* Registros de control del Watchdog */
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#define MCFSIM_WRRR 0x280
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#define MCFSIM_WIRR 0x284
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#define MCFSIM_WCR 0x288
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#define MCFSIM_WER 0x28C
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/*******************************************/
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/* Registros del modulo PWM */
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/*******************************************/
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#define MCFSIM_PWCR0 0x00C0
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#define MCFSIM_PWCR1 0x00C4
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#define MCFSIM_PWCR2 0x00C8
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#define MCFSIM_PWWD0 0x00D0
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#define MCFSIM_PWWD1 0x00D4
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#define MCFSIM_PWWD2 0x00D8
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/* Correspondencia entre frecuencias y divisor a configurar */
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/* Los módulos PWM generan una señal con un periodo obtenido */
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/* de dicidir la frecuencia de reloj del sistema (66 MHz) */
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/* de la siguiente manera: */
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/* */
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/* Frec = (66 MHz) / 256*(2^(X)) ,, X = Divisor a configurar */
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/* */
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#define PWM_258KHZ 0x00
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#define PWM_129KHZ 0x01
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#define PWM_64KHZ 0x02
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#define PWM_32KHZ 0x03
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#define PWM_16KHZ 0x04
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#define PWM_8KHZ 0x05
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#define PWM_4KHZ 0x06
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#define PWM_2KHZ 0x07
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#define PWM_1KHZ 0x08
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#define PWM_512HZ 0x09
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#define PWM_258HZ 0x0A
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#define PWM_129HZ 0x0B
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#define PWM_66HZ 0x0C
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#define PWM_34HZ 0x0D
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#define PWM_17HZ 0x0E
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#define PWM_9HZ 0x0F
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/*
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* Macro to get and set IMR register. It is 16 bits on the 5272.
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*/
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#define BASE_PUERTO0 0x30000000
/* Direccion del puerto 0 */
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#define BASE_PUERTO_S 0x40000000
/* Direccion del puerto S */
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#define BASE_PUERTO_E 0x50000002
/* Direccion del puerto E */
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/*******************************************/
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/* Registros del modulo QSPI */
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/*******************************************/
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#define MCFSIM_QMR 0x00A0
/* modo */
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#define MCFSIM_QDLYR 0x00A4
/* retardo */
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#define MCFSIM_QWR 0x00A8
/* wrap */
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#define MCFSIM_QIR 0x00aC
/* interrupción */
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#define MCFSIM_QAR 0x00B0
/* dirección */
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#define MCFSIM_QDR 0x00B4
/* dato */
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#define QSPI_TX_RAM_START 0x00
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#define QSPI_RX_RAM_START 0x10
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#define QSPI_COMMAND_RAM_START 0x20
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/****************************************************************************/
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#endif
/* m5272_h */
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m5272.h
Generado el Miércoles, 13 de Mayo de 2015 02:55:33 para XT-26 por
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